The JTAGulator is tool to assist identifying JTAG and USART pins.
JTAG (named after the Joint Test Action Group) is an industry standard for verifying designs and testing printed circuit boards after manufacture.
- JTAG allows for many applications
- Boundary Scan (read and set values of pin)
- Debugging of hardware / software
- Program / Modify memory
- Chips can be daisy chained, so you can access multiple chips through one interface
- JTAG consist of 4 essential signals
- TCK ... Test Clock
- TMS ... Test Mode Select (Steuerung)
- TDI ... Test Data In
- TDO ... Test Data Out
- additional signals
- Vcc ... 3.3V
- GND ... ground
- TRST .. test reset (low active)
- RST ... system reset (low active)
Good video about the JTAG interface: EEVblog #499 - What is JTAG and Boundary Scan?
Manufactures have different Pin Layout, for Cortex Connectors it looks like this:
Since JTAG pins are not always labelled, they can be hard to find. This is when the JTAGulator comes into play.
You connect the channels of the JTAGulator to different test pins on the hardware you want to analyze.
The JTAGulator test each individual pins and tries to find JTAG connections. If found it will output the correct JTAG pins.
- Connect the JTAGulator via serial to the computer
- 115200 bps, 8 data bits, no parity, 1 stop bit
- Linux: you can use minicom
- Windows: you can use Putty
- You should see following output:
- Connect the JTAGulator to the test-device
- Connect the JTAGulator Ground (GND) to the GND of the hardware you want to analyze.
- Connect CHx from the JTAGulator to some pins on the hardware which may be JTAG pins (start from CH0). Do not use the VADJ pin on the JTAGualtor (VADJ is the output from the PWM/op amp hardware on the JTAGulator that's used to create the target system voltage and drive the on-board level translators.)